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Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor

机译:电荷保持晶体管,存储单元的阵列以及形成电荷保持晶体管的方法

摘要

A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.
机译:电荷保持晶体管包括控制栅极和与控制栅极并排的栅极间电介质。晶体管的电荷存储节点在栅极间电介质旁边包括第一半导体材料。电荷俘获材料的孤岛与第一半导体材料并排。防氧化材料位于岛的旁边。第二半导体材料在抗氧化材料旁边,并且具有与抗氧化材料不同的组成。隧道电介质位于电荷存储节点旁边。通道材料位于隧道电介质旁边。公开了包括方法的另外的实施例。

著录项

  • 公开/公告号US9159845B2

    专利类型

  • 公开/公告日2015-10-13

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US201313894481

  • 发明设计人 D. V. NIRMAL RAMASWAMY;

    申请日2013-05-15

  • 分类号H01L21/336;H01L29/788;H01L29/02;H01L29/66;H01L29/792;H01L29/423;H01L27/115;

  • 国家 US

  • 入库时间 2022-08-21 15:23:27

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