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Non-binary decoder architecture and control signal logic for reduced circuit complexity
Non-binary decoder architecture and control signal logic for reduced circuit complexity
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机译:非二进制解码器架构和控制信号逻辑,可降低电路复杂度
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摘要
A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log2X inputs for receiving the clock signal inputs.
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