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NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC
NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC
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机译:结合粗略ADC和SAR ADC的新颖技术
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摘要
A successive approximation register analog to digital converter (SAR ADC) is disclosed. The SAR ADC receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.
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机译:公开了一种逐次逼近寄存器模数转换器(SAR ADC)。 SAR ADC接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。电荷共享DAC包括一个MSB(最高有效位)电容器阵列和LSB(最低有效位)电容器阵列。过零检测器耦合到电荷共享DAC。过零检测器产生数字输出。粗略的ADC(模数转换器)接收输入电压并生成粗略的输出。预定义的偏移被添加到粗略ADC的残差。逐次逼近寄存器(SAR)状态机耦合到粗略ADC和过零检测器,并生成多个控制信号。多个控制信号在采样模式,纠错模式和转换模式下操作电荷共享DAC。
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