IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration

摘要

A coarse analog-to-digital converter (ADC) is used as the reference path to resolve the input interference problem in correlation-based background calibration of multistep ADCs. A 16-bit successive-approximation-register (SAR) ADC employing a subbinary architecture is calibrated with an 8-bit reference path, achieving a nearly 20 × reduction in convergence time and greatly improved steady-state linearity performance in simulation. The SAR ADC bit-weight calibration is based on the principle of internal redundancy dithering (IRD), a technique in which the bit decision thresholds are dithered by a pseudorandom bit sequence (PRBS) within the redundancy region. Aided by the coarse reference ADC, behavioral simulation shows that 89-dB signal-to-noise plus distortion ratio and the 115-dB spurious-free dynamic range (SFDR) are achievable with the proposed calibration for a SAR ADC with 1% digital-to-analog converter mismatch errors.