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Process for Fabricating a Ridge Pin Junction Comprising Spaced Apart Doped Regions, Application to the Fabrication of Electro-optical Modulators and Photodetectors

机译:包括间隔分开的掺杂区的脊形销结的制造方法,在电光调制器和光电探测器的制造中的应用

摘要

The invention relates to a process for fabricating a semiconductor ridge pin junction (20, 21). According to the invention, judicious choices are made when defining hard masks and the sequence in which resist masks are formed for implantation (doping) and etching, which choices enable the conventional photolithography technique to be used despite the low precision of mask alignment (±100 nm) relative to underlying regions.;By virtue of the process according to the invention, a ridge pin junction is formed, at lower cost and with shorter production times than in the prior art, with doped regions precisely spaced apart from the edge of the ridge.
机译:本发明涉及一种制造半导体脊形销结( 20、21 )的方法。根据本发明,在定义硬掩模以及形成用于注入(掺杂)和蚀刻的抗蚀剂掩模的顺序时做出明智的选择,尽管掩模对准的精度低(±100),该选择仍能够使用传统的光刻技术。相对于下面的区域,通过本发明的方法,与现有技术相比,以较低的成本和更短的生产时间形成了脊形销结,其中掺杂区与晶片的边缘精确地间隔开。岭。

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