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Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors
Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors
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机译:门控双极结晶体管,存储器阵列和形成门控双极结晶体管的方法
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摘要
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
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