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RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN
RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN
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机译:可重新配置的内存接口电路,支持内置的内存扫描链
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摘要
A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.
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