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Sustainable Differentially Reliable Architecture for Dark Silicon
Sustainable Differentially Reliable Architecture for Dark Silicon
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机译:深色硅的可持续差异可靠架构
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摘要
For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map module maps the process threads to the plurality of cores based on at least one of the expected energy efficiency and the WAC to satisfy a mapping policy. A specified number of the plurality of cores is not powered.
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