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Package substrate with high density interconnect design to capture conductive features on embedded die

机译:具有高密度互连设计的封装基板,可捕获嵌入式芯片上的导电特征

摘要

Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.
机译:本公开的实施例针对用于嵌入在包括桥的封装组件中的互连结构的技术和配置。在一个实施例中,封装组件可以包括封装基板,嵌入在封装基板中并且包括桥基板的桥以及包括通孔的互连结构,该通孔延伸穿过封装基板进入桥基板的表面并且被配置为与之接合。设置在桥接基板表面上或下方的导电部件。互连结构可以被配置为在导电特征和安装在封装基板上的管芯之间路由电信号。可以描述和/或要求保护其他实施例。

著录项

  • 公开/公告号US9119313B2

    专利类型

  • 公开/公告日2015-08-25

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201313870874

  • 申请日2013-04-25

  • 分类号H05K1/18;H05K1/11;H05K3/40;

  • 国家 US

  • 入库时间 2022-08-21 15:20:19

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