Hardware architecture and implementation of low power layered multi-level LDPC decoder

摘要

A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.