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Snr improvement circuit, synchronization information detection circuit, communication device, snr improvement method, and synchronization information detection method

机译:Snr改善电路,同步信息检测电路,通信装置,snr改善方法以及同步信息检测方法

摘要

A technique capable of improving a packet catch rate when applied to a communication device, for example. An SNR improvement circuit for improving an SNR of an input signal includes a delay unit for delaying the input signal to generate one or more delay signals, and an adder for adding the one or more delay signals and the input signal before being delayed. The input signal contains a periodic signal in which the same signal is repeated a predetermined number of times with a predetermined period. The delay unit generates the one or more delay signals with delay time which is α times (α is a natural number, and is set at different values with respect to two or more delay signals) longer than the predetermined period.
机译:例如,一种当应用于通信设备时能够提高分组捕获率的技术。一种用于改善输入信号的SNR的SNR改善电路,包括:延迟单元,其用于延迟输入信号以生成一个或多个延迟信号;加法器,其用于在延迟之前将一个或多个延迟信号与输入信号相加。输入信号包含周期性信号,其中相同信号以预定周期重复预定次数。延迟单元以比预定周期长α倍的延迟时间(α是自然数,并且对于两个或多个延迟信号被设置为不同的值)来生成一个或多个延迟信号。

著录项

  • 公开/公告号US9178686B2

    专利类型

  • 公开/公告日2015-11-03

    原文格式PDF

  • 申请/专利权人 HANDA CHEN;

    申请/专利号US201213983924

  • 发明设计人 HANDA CHEN;

    申请日2012-01-20

  • 分类号H04B17/02;H04L7;H04L7/04;H04L27/26;

  • 国家 US

  • 入库时间 2022-08-21 15:19:46

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