首页> 外国专利> Integration of an NPN device with phosphorus emitter and controlled emitter-base junction depth in a BiCMOS process

Integration of an NPN device with phosphorus emitter and controlled emitter-base junction depth in a BiCMOS process

机译:在BiCMOS工艺中将NPN器件与磷发射极集成在一起,并控制发射极-基极的结深

摘要

According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
机译:根据一个示例性实施例,一种异质结双极晶体管包括位于衬底上的基极。异质结双极晶体管可以是例如NPN硅锗异质结双极晶体管。异质结双极晶体管还包括位于基极上的盖层,其中该盖层包括势垒区域。势垒区可以包括碳并且具有厚度,其中势垒区的厚度确定异质结双极晶体管的发射极结的深度。势垒区厚度的增加会导致发射极-基极结的深度减小。根据该示例性实施例,异质结双极晶体管还包括位于盖层上方的发射极,其中该发射极包括可以是磷的发射极掺杂剂。覆盖层的势垒区域中的扩散阻滞剂阻止发射极掺杂剂的扩散。

著录项

  • 公开/公告号US8987785B2

    专利类型

  • 公开/公告日2015-03-24

    原文格式PDF

  • 申请/专利权人 GREG D. UREN;

    申请/专利号US20090321410

  • 发明设计人 GREG D. UREN;

    申请日2009-01-21

  • 分类号H01L29/739;H01L29/737;H01L21/8249;H01L27/06;H01L29/08;H01L29/66;

  • 国家 US

  • 入库时间 2022-08-21 15:19:02

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