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Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods

机译:具有与较小尺寸的柱子相邻的存储单元的沟道长度大于与较大尺寸的柱子相邻的存储单元的沟道和方法的存储阵列

摘要

The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.
机译:本公开涉及存储器阵列和方法。一种这样的存储器阵列具有基本垂直的柱。与其中柱具有第一尺寸的柱相邻的存储单元的沟道长度比在其柱具有第二尺寸大于第一尺寸的柱的相邻存储单元的沟道长度大。

著录项

  • 公开/公告号US9076824B2

    专利类型

  • 公开/公告日2015-07-07

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC;

    申请/专利号US201213667649

  • 发明设计人 KOJI SAKUI;PETER FEELEY;

    申请日2012-11-02

  • 分类号G11C16/04;H01L29/66;H01L29/788;H01L29/792;H01L27/115;

  • 国家 US

  • 入库时间 2022-08-21 15:17:36

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