首页> 外国专利> LAYOUTS FOR THE MONOLITHIC INTEGRATION OF CMOS AND DEPOSITED PHOTONIC ACTIVE LAYERS

LAYOUTS FOR THE MONOLITHIC INTEGRATION OF CMOS AND DEPOSITED PHOTONIC ACTIVE LAYERS

机译:CMOS的整体积分布局和沉积的光子有源层

摘要

Several detailed layout designs are disclosed, for the monolithic integration of avalanche devices in large arrays, that can be operated as Avalanche Photo-Diodes (APDs) or Avalanche Light Emitting Diodes (ALEDs) depending only on the applied bias conditions, which can be software-controlled from peripheral circuitry. If the deposited films have direct bandgaps, then the devices can emit light even in the absence of avalanche operation. In particular, the layouts according to the invention comprise a sensor/emitter matrix achieved through the replication of basic Pixel/Lixel cells.
机译:公开了几种详细的布局设计,用于大阵列中雪崩器件的单片集成,可以仅根据所施加的偏置条件将其用作雪崩光电二极管(APD)或雪崩发光二极管(ALED),这可以是软件由外围电路控制。如果沉积的薄膜具有直接的带隙,那么即使没有雪崩操作,该设备也可以发光。特别地,根据本发明的布局包括通过复制基本像素/像素单元而获得的传感器/发射器矩阵。

著录项

  • 公开/公告号EP1794797B1

    专利类型

  • 公开/公告日2015-09-09

    原文格式PDF

  • 申请/专利权人 QUANTUM SEMICONDUCTOR LLC;

    申请/专利号EP20050773953

  • 发明设计人 AUGUSTO CARLOS J.R.P.;

    申请日2005-07-28

  • 分类号H01L27/146;H01L27/15;

  • 国家 EP

  • 入库时间 2022-08-21 15:09:00

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号