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LAYOUTS FOR THE MONOLITHIC INTEGRATION OF CMOS AND DEPOSITED PHOTONIC ACTIVE LAYERS
LAYOUTS FOR THE MONOLITHIC INTEGRATION OF CMOS AND DEPOSITED PHOTONIC ACTIVE LAYERS
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机译:CMOS的整体积分布局和沉积的光子有源层
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摘要
Several detailed layout designs are disclosed, for the monolithic integration of avalanche devices in large arrays, that can be operated as Avalanche Photo-Diodes (APDs) or Avalanche Light Emitting Diodes (ALEDs) depending only on the applied bias conditions, which can be software-controlled from peripheral circuitry. If the deposited films have direct bandgaps, then the devices can emit light even in the absence of avalanche operation. In particular, the layouts according to the invention comprise a sensor/emitter matrix achieved through the replication of basic Pixel/Lixel cells.
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