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METHOD FOR ANALYZING CMOS DYNAMIC POWER DISSIPATION USING TEMPORAL PARALLEL SIMULATION
METHOD FOR ANALYZING CMOS DYNAMIC POWER DISSIPATION USING TEMPORAL PARALLEL SIMULATION
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机译:基于时间并行仿真的CMOS动态功耗分析方法
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摘要
The present invention relates to a method for rapidly and accurately predicting dynamic power consumption through a simulation. Switching frequency information required for predicting dynamic power consumption is collected in parallel when at least two simulators are independently performed in parallel through a temporal parallel simulation.
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