A phase error detector 23 is provided with: an error component detector 31 for detecting an error component signal Pe representing a phase error in a received baseband signal; a signal classification unit 51 for classifying the error component signal Pe in one of a number of phase areas delimiting the phase error detection area; a retry controller 52 for determining whether the error component signal Pe has been classified in at least a certain phase range among the number of phase ranges for a designated number of times; and an update processor 53 for reducing the detection range when it is determined that the error component signal Pe has been classified for the designated number of times in the determined phase range; and a signal output unit 43 for setting a value in the determined phase range as a stable state value of the phase error when it is determined that the determined phase range satisfies a prescribed inclusion condition.
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