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INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANNABLE FLIP FLOPS AND METHOD OF OPERATING THEREOF
INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANNABLE FLIP FLOPS AND METHOD OF OPERATING THEREOF
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机译:具有双边触发的可缩放翻转触发器的扫描链集成电路及其操作方法
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摘要
An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
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