首页> 外国专利> Reduced defect densities in graded buffer layers by tensile strained interlayers

Reduced defect densities in graded buffer layers by tensile strained interlayers

机译:通过拉伸应变中间层降低渐变缓冲层中的缺陷密度

摘要

A semiconductor stack includes a substrate; a first semiconductor layer disposed on the substrate; a tensile strained interlayer layer disposed on the first semiconductor layer; and a second semiconductor layer disposed on the strained interlayer; wherein the difference in strain between the first semiconductor layer and the tensile strained interlayer is about 1 to about 2%.
机译:半导体叠层包括衬底;设置在基板上的第一半导体层;拉伸应变中间层设置在第一半导体层上;第二半导体层设置在应变夹层上。其中第一半导体层和拉伸应变中间层之间的应变差为约1%至约2%。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号