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Low-power, high-speed successive approximation register analog-to-digital converter and conversion method using the same
Low-power, high-speed successive approximation register analog-to-digital converter and conversion method using the same
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机译:低功耗,高速逐次逼近寄存器模数转换器及其转换方法
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摘要
Provided is a low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The low-power, high-speed SAR ADC includes a bootstrapping unit configured to receive inputs of first and second analog signals, a double-bit output SAR analog-to-digital conversion unit configured to output a two-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit, and a single-bit output SAR analog-to-digital conversion unit configured to output a one-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit.
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