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MICROARCHITECTURE FOR FLOATING POINT FUSED MULTIPLY-ADD WITH EXPONENT SCALING

机译:浮点熔合指数缩放的微体系结构

摘要

Systems and methods for implementing a floating point fused multiply and accumulate with scaling (FMASc) operation. A floating point unit receives input multiplier, multiplicand, addend, and scaling factor operands. A multiplier block is configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product. Alignment logic is configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand, and accumulation logic is configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit. Normalization and rounding are performed on the result, avoiding rounding during intermediate stages.
机译:用于实现浮点融合乘和累加缩放(FMASc)操作的系统和方法。浮点单元接收输入乘数,被乘数,加数和缩放因子操作数。乘法器块被配置为将乘法器和被乘数的尾数相乘以生成中间乘积。对齐逻辑被配置为基于比例因子和加数,乘数和被乘数的指数将加数与中间乘积进行预对齐,累积逻辑被配置为与中间乘积相加或减去预对齐的加数的尾数乘积以获得浮点单位的结果。对结果进行归一化和舍入,避免在中间阶段进行舍入。

著录项

  • 公开/公告号US2015347089A1

    专利类型

  • 公开/公告日2015-12-03

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号US201514824547

  • 发明设计人 LIANG-KAI WANG;

    申请日2015-08-12

  • 分类号G06F7/483;

  • 国家 US

  • 入库时间 2022-08-21 14:33:40

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