Decimal floating-point fused multiply-add with redundant internal encodings

摘要

Decimal floating-point (DFP) arithmetic has attracted attention in the applications of financial and commercial computing. However, the processing efficiency of DFP is still far away from that of binary designs. On the other hand, a floating-point fused multiply-add (FMA) function is widely used in many processors within functional iterations to implement division, square root, and many other functions due to the better accuracy achieved by a single rounding of continuous multiplication and addition. In this work, a new architecture of FMA is proposed to speed up the DFP processing. Compared with previous architectures, first, the proposed design applies a specific decimal redundant encoding system. The circuits to decide and shift the rounding position on a redundant result are therefore simplified. Second, the only digit-set conversion in the entire design is combined with the rounding operation to further reduce the critical path. Third, the techniques applied in different previous FMAs are merged in the proposed design. In addition the multiplier and adder referred to the previous designs are further optimised. Consequently, compared with the fastest previous design, the synthesis results show about 33.7% speed advantage and about 16.6% area advantage.