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RECONFIGURABLE FRACTIONAL DIVIDER

机译:可重构分数除法

摘要

Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.
机译:提供了可重新配置的分频器电路的方面。可重新配置的分频器可以包括被配置为接收输入信号的分频器。分频器还可以包括延迟电路,该延迟电路被配置为接收由分频器产生的分频信号。分频器还可以包括倍频器,其被配置为基于由延迟电路产生的延迟信号来产生输出信号,其中,延迟电路被配置为接收输出信号。

著录项

  • 公开/公告号US2015349782A1

    专利类型

  • 公开/公告日2015-12-03

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号US201414488248

  • 发明设计人 HUNG-CHUAN PAI;GANG ZHANG;

    申请日2014-09-16

  • 分类号H03K21/02;H04B1/40;

  • 国家 US

  • 入库时间 2022-08-21 14:33:08

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