Systems and methods of low power decimation filter for sigma delta ADC

摘要

Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter response. The input data may be treated as 0 and 1 instead of −1 and +1. The symmetry of the sinc filter may be exploited since the data across different polyphases are combined. The addition of the symmetric data and coefficient multiplication may be replaced with simple muxing based on two bits and the use of unsigned logic for all adders following coefficient multiplication as both data and coefficient are non-negative.