首页> 外国专利> Instruction scheduling for reducing register usage based on dependence depth and presence of sequencing edge in data dependence graph

Instruction scheduling for reducing register usage based on dependence depth and presence of sequencing edge in data dependence graph

机译:基于依赖深度和数据依赖图中序列边缘的存在来减少寄存器使用的指令调度

摘要

A method, computer program product, and system are provided for scheduling a plurality of instructions in a computing system. For example, the method can generate a plurality of instruction lineages, in which the plurality of instruction lineages is assigned to one or more registers. Each of the plurality of instruction lineages has at least one node representative of an instruction from the plurality of instructions. The method can also determine a node order based on respective priority values associated with each of the nodes. Further, the method can include scheduling the plurality of instructions based on the node order and the one or more registers assigned to the one or more registers.
机译:提供了一种用于调度计算系统中的多个指令的方法,计算机程序产品和系统。例如,该方法可以生成多个指令沿袭,其中多个指令沿袭被分配给一个或多个寄存器。多个指令谱系中的每一个具有代表来自多个指令的指令的至少一个节点。该方法还可以基于与每个节点相关联的相应优先级值来确定节点顺序。此外,该方法可以包括基于节点顺序和分配给一个或多个寄存器的一个或多个寄存器来调度多个指令。

著录项

  • 公开/公告号US9417878B2

    专利类型

  • 公开/公告日2016-08-16

    原文格式PDF

  • 申请/专利权人 GANG CHEN;SRINIVASA B. YADAVALLI;

    申请/专利号US201213435456

  • 发明设计人 GANG CHEN;SRINIVASA B. YADAVALLI;

    申请日2012-03-30

  • 分类号G06F9/30;G06F9/38;G06F9/45;

  • 国家 US

  • 入库时间 2022-08-21 14:32:17

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