Graded aluminum—gallium—nitride and superlattice buffer layer for III-V nitride layer on silicon substrate

摘要

The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from Al_xGa_1-xN/Al_yGa_1-yN layer pairs.