Digital PLL with hybrid phase/frequency detector and digital noise cancellation

摘要

Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ PFD). A hybrid 2nd-order ΔΣ PFD may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ΔΣ quantization noise. The implementation of low complexity ΔΣ PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).