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Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts
Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts
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机译:垂直场效应晶体管,栅电极与源极/漏极触点之间的交叠可控
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摘要
An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.
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