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Vertical Field-Effect Transistor having a Dielectric Spacer between a Gate Electrode Edge and a Self-Aligned Source/Drain Contact
Vertical Field-Effect Transistor having a Dielectric Spacer between a Gate Electrode Edge and a Self-Aligned Source/Drain Contact
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机译:垂直场效应晶体管,在栅电极边缘和自对准源极/漏极触点之间具有介电垫片
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摘要
Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.
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