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Transistors having one or more dummy lines with different collective widths coupled thereto

机译:具有连接到其上的不同集体宽度的一条或多条伪线的晶体管

摘要

In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.
机译:在一个实施例中,晶体管的阵列具有耦合到第一晶体管的第一线。第一线在与第一晶体管相继相邻的第二晶体管上方和与第二晶体管相继相邻的第三晶体管上方延伸。第二条线连接到第二晶体管并在第三晶体管上延伸。一个或多个第一虚设线耦合到第一线并从第一晶体管延伸到第二晶体管。一个或多个第二虚设线耦合到第二线并且从第二晶体管延伸到第三晶体管。一条或多条第一虚拟线的总宽度大于一条或多条第二虚拟线的总宽度。

著录项

  • 公开/公告号US9287260B1

    专利类型

  • 公开/公告日2016-03-15

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US201414478220

  • 发明设计人 MICHAEL A. SMITH;VLADIMIR MIKHALEV;

    申请日2014-09-05

  • 分类号H01L27/088;H01L27/115;H01L23/528;H01L27/02;

  • 国家 US

  • 入库时间 2022-08-21 14:31:20

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