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Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
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机译:具有高级仲裁,虚拟化和EDC的多主机缓存一致性推测支持内存控制器
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摘要
This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.
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