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Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
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机译:具有可选确认的无序一致性事务完成的一致性缓存系统
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摘要
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
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