Inter-set wear-leveling for caches with limited write endurance

摘要

A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N²−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.