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Inter-set wear-leveling for caches with limited write endurance
Inter-set wear-leveling for caches with limited write endurance
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机译:写入损耗有限的高速缓存的组间损耗均衡
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摘要
A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N2−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.
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