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Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance
Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance
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机译:基于改进的图案化晶圆几何尺寸测量的设计改进,可实现最佳的集成芯片制造性能
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摘要
Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.
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