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Timing bottleneck analysis across pipelines to guide optimization with useful skew
Timing bottleneck analysis across pipelines to guide optimization with useful skew
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机译:跨管道的时间瓶颈分析,以有用的偏差指导优化
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摘要
Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of the circuit design based on the set of aggregate slacks.
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