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System for reducing peak power during scan shift at the global level for scan based tests
System for reducing peak power during scan shift at the global level for scan based tests
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机译:用于在基于扫描的测试的全局级别上降低扫描移位期间的峰值功率的系统
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摘要
A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.
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