Method for creating a reliable phase-locked loop in a ruggedized or harsh environment

摘要

A phase-locked loop (PLL) circuit system includes first, second, and third PLL circuits, first, second, and third multiplexer circuits coupled to the first, second, and third PLL circuits, and a majority voter circuit coupled to the first, second, and third PLL circuits, wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit. Each PLL circuit includes a first input for receiving a reference clock signal; a second input for receiving a feedback clock signal; a first output for providing an output clock signal; a second output for providing a lock signal; and a return path coupled between the first output and the second input. The return path can be a direct connection or a logic circuit. Each multiplexer circuit includes three lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.