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Fet structure for minimum size length/width devices for performance boost and mismatch reduction
Fet structure for minimum size length/width devices for performance boost and mismatch reduction
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机译:Fet结构,用于最小尺寸的长度/宽度设备,以提高性能并减少失配
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摘要
Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.
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