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Handling virtual memory address synonyms in a multi-level cache hierarchy structure

机译:在多级缓存层次结构中处理虚拟内存地址同义词

摘要

Handling virtual memory address synonyms in a multi-level cache hierarchy structure. The multi-level cache hierarchy structure having a first level, L1 cache, the L1 cache being operatively connected to a second level, L2 cache split into a L2 data cache directory and a L2 instruction cache. The L2 data cache directory including directory entries having information of data currently stored in the L1 cache, the L2 cache being operatively connected to a third level, L3 cache. The first level cache is virtually indexed while the second and third levels are physically indexed. Counter bits are allocated in a directory entry of the L2 data cache directory for storing a counter number. The directory entry corresponds to at least one first L1 cache line. A first search is performed in the L1 cache for a requested virtual memory address, wherein the virtual memory address corresponds to a physical memory address tag at a second L1 cache line.
机译:在多级缓存层次结构中处理虚拟内存地址同义词。具有第一级L1高速缓存的多级高速缓存层次结构,L1高速缓存可操作地连接到第二级,L2高速缓存分为L2数据高速缓存目录和L2指令高速缓存。 L2数据高速缓存目录包括具有当前存储在L1高速缓存中的数据信息的目录条目,L2高速缓存可操作地连接到第三级L3高速缓存。对第一级缓存进行虚拟索引,而对第二级和第三级进行物理索引。在L2数据高速缓存目录的目录条目中分配了计数器位,用于存储计数器号。该目录条目对应于至少一个第一L1高速缓存行。在L1高速缓存中对请求的虚拟内存地址执行第一次搜索,其中虚拟内存地址对应于第二个L1高速缓存行中的物理内存地址标签。

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