A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell

摘要

This paper reports a 1-V 128-kb four-way set-associative CMOSncache memory implemented by a 0.18-Μm CMOS technology usingnwordline-oriented tag-compare (WLOTC) structure with the 10-transistorntag cell usually for content-addressable memory (CAM) for low-voltagenlow-power VLSI system application. Owing to the WLOTC structure with thenCAM 10-transistor tag cell for accommodating the one-step hit/missngeneration and the dynamic pulse generators for realizing read-enablensignals, a small hit access time (3.5 ns), low power consumption (4.1 mWnat 50 MHz), and good expansion capability without sacrificing speed havenbeen obtained