VERTICAL TUNNELLING FIELD-EFFECT TRANSISTOR AND PREPARATION METHOD THEREFOR

摘要

Provided are a vertical tunnelling field-effect transistor and a preparation method therefor. The vertical tunnelling field-effect transistor comprises: a source region (1), a first epitaxial layer (2), a gate dielectric layer (3), a gate region (4) and two drain regions (5). A first groove (11) is provided in the source region. A second groove (21) is provided on the first epitaxial layer, and the first epitaxial layer forms a tunnelling channel between the gate region and the source region. Both the gate dielectric layer and the gate region are provided in the second groove. The two drain regions are respectively provided at two opposite sides outside the second groove. Tunnelling can occur in conduction electrons in an area, overlapped with the gate region, of the first groove of the source region, i.e. an overlapping area between the source region and the gate region is enlarged using the first groove, so that a tunnelling area is enlarged. The first epitaxial layer can form the channel between the gate region and the source region, which involves linear tunnelling, and when the electric field direction of the gate region and the electron tunnelling direction of the source region are on the same line, the tunnelling probability is high, thereby improving a tunnelling current.