LOW POWER WIDEBAND NON-COHERENT BPSK DEMODULATOR TO ALIGN THE PHASE OF SIDEBAND DIFFERENTIAL OUTPUT COMPARATORS FOR REDUCING JITTER, USING 1ST ORDER SIDEBAND FILTERS WITH PHASE 0 DEGREE ALIGNMENT

摘要

An embodiment of the present invention relates to a method for low-power broadband asynchronous BPSK demodulation and configuration of a circuit for the same. Provided may be a low-power broadband asynchronous binary phase shift keying (BPSK) demodulation circuit comprising: a sideband digital separation unit which separates a modulated signal into an upper sideband and a lower sideband by using a first order high-pass filter and a first order low-pass filter whose blocking frequencies are carrier frequencies, and digitizes the upper sideband and the lower sideband to have a positive phase and a negative phase, wherein jitter is minimized by using two pairs of signals in which digital output of a lower sideband comparator has a phase identical to that of digital output of an upper sideband comparator; an upper sideband positive phase signal delay and phase detection clock unit which generates a signal by delaying the upper sideband positive phase digital signal by /2 of the corresponding carrier frequency, aligns a phase difference between the delayed digital signal and the lower sideband positive phase digital signal to 0, and generates a first symbol edge signal including a glitch adapted to be used as a detection clock for data demodulation; an upper sideband negative phase signal delay and phase detection clock unit which generates a signal by delaying the upper sideband negative phase digital signal by /2 of the corresponding carrier frequency, aligns a phase difference between the delayed digital signal and the lower sideband negative phase digital signal to 0, and generates a second symbol edge signal including a glitch; a data demodulation unit which reduces the glitches of signals having the glitches via an AND gate, and demodulates digital data by synchronizing the lower sideband positive phase digital signal with a symbol edge clock having no glitch via a deglitch filter; and a data clock restoration unit which generates a data clock by using the lower sideband positive phase digital signal and a data signal.