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Fabrication method of metal gates-embedded nanochannel

机译:嵌入金属门的纳米通道的制备方法

摘要

The present invention relates to a method of manufacturing a nanochannel including a metal gate using chemical vapor deposition and planarization processes. A method of fabricating a nanochannel that includes a metal gate in accordance with one aspect of the present invention includes a first step of forming a first layer 102 on an upper surface of a substrate 101, Forming a first layer 102 on which the second layer 103 is not formed by using the second layer 103 as an etch mask; A third step of removing the second layer 103 and a fourth step of forming a third layer 104 on the substrate 101 and the first layer 102 using an isotropic deposition process The third layer 104 on the substrate 101 and the first layer 102 is removed and the third layer 104 on the side of the first layer 101 is removed using an anisotropic etching process, A fourth step of forming a fourth layer 105 on the substrate 101, the first layer 102 and the third layer 104, the seventh step of leaving only the first layer 102 and the third layer 104, An eighth step of planarizing the layer 104 so as to be exposed, A ninth step of forming a fifth layer 106 on the first layer 102, the third layer 104 and the fourth layer 105, the ninth step of forming the fifth layer 106 on the third layer A third layer 104, a fourth layer 106, and a third layer 104 using an isotropic deposition process to remove a portion of the fifth layer 106 so as to be perpendicular to the longitudinal direction of the first layer 102, A third layer 104, and a fourth layer 106 are formed by using an anisotropic etching process in an eleventh step of forming a sixth layer 107 on the first layer 105 and the fifth layer 106 Removing the sixth layer 107 on the fifth layer 106 and leaving only the sixth layer 107 on the side of the fifth layer 106; A seventh step of forming a seventh layer 108 on the third layer 104, the fourth layer 105, the fifth layer 106 and the sixth layer 107; The sixth layer 107 is etched to remove the exposed sixth layer 107, and the fifth layer 106 and the seventh layer 108 are used as an etching mask. And the substrate 1 The first layer 102, the third layer 104 and the fourth layer 105 are anisotropically etched so that the first layer 102, the third layer 104 and the fourth layer 105 are exposed so that the first layer 102, And removing the fifth layer 106 and the seventh layer 108 so that the fourth layer 105 is exposed.
机译:本发明涉及一种使用化学气相沉积和平坦化工艺制造包括金属栅极的纳米通道的方法。根据本发明的一个方面,一种制造包括金属栅极的纳米通道的方法包括第一步:在衬底101的上表面上形成第一层102,在其上形成第二层103的第一层102。不通过使用第二层103作为蚀刻掩模来形成;使用各向同性沉积工艺去除第二层103的第三步骤和在衬底101和第一层102上形成第三层104的第四步骤。去除衬底101上的第三层104和第一层102,并且使用各向异性蚀刻工艺去除第一层101侧上的第三层104。第四步骤是在基板101,第一层102和第三层104上形成第四层105,第七步骤仅留下第一层102和第三层104,将层104平坦化以使其暴露的第八步骤,在第一层102,第三层104和第四层105上形成第五层106的第九步骤,第九层。在第三层上形成第五层106的步骤使用各向同性沉积工艺在第三层104,第四层106和第三层104上去除第五层106的一部分以使其垂直于纵向冷杉在第一个步骤中,在第一层105上形成第六层107并在第五层106上去除第六层107,通过各向异性刻蚀工艺形成t层102,第三层104和第四层106。层106并且仅在第五层106的侧面上留下第六层107;第七步骤,在第三层104,第四层105,第五层106和第六层107上形成第七层108;蚀刻第六层107以去除暴露的第六层107,并且第五层106和第七层108用作蚀刻掩模。并且基板1各向异性地蚀刻第一层102,第三层104和第四层105,从而露出第一层102,第三层104和第四层105,使得第一层102,并去除第五层。层106和第七层108,从而暴露出第四层105。

著录项

  • 公开/公告号KR101579307B1

    专利类型

  • 公开/公告日2016-01-04

    原文格式PDF

  • 申请/专利权人 나노칩스(주);

    申请/专利号KR20120080414

  • 发明设计人 최중범;이종진;

    申请日2012-07-24

  • 分类号H01L21/336;H01L21/205;H01L21/304;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 14:13:13

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