MULTI-TIME PROGRAMMABLE MEMORY FOR POWER MANAGEMENT IC

摘要

An embodiment of the present invention implements a program (write/erase) type multi-time programmable (MTP) cell using boost voltage and negative voltage which are pumping voltage with respect to the MTP cell, to enable an MTP design without using a high voltage (HV) element based on a BCD backbone process. Another embodiment of the present invention implements that a tunnel gate oxide and a sense transistor are merged into one to reduce a size of the MTP cell, and implements a three-stage voltage level transistor circuit, a VNN charge pumping circuit, and a VNN precharge circuit which assure reliability of an element having 5V of operating voltage. The other embodiment of the present invention implements a dual memory structure where an MTP memory area is divided into a designer memory area and a user area. A memory for a power management IC (PMIC) includes: an MTP memory; a control logic unit; a control gate operation unit; a bit line switch; a buffer for parallel data; a buffer for byte data; and a DC-DC converter.