Asynchronous sar - adu with a binary scaled redundancy

摘要

Representative implementations of devices and methods are the analog - digital - reaction time-discrete analog inputs ready. A redundant binary scaled capacitance circuit arrangement with the use of a method of successive approximation, a rapid and power efficient adu with improved error correction providing. For example, a capacitor circuit arrangement for the successive approximation a plurality of capacitance circuit arrangements of with binary bitgewichten comprise. In one implementation, the process comprises the processing of the capacitances in successive cycles, wherein each cycle of a binary error correction code is generated, the more than one bit of the digital output represents.