Serializer and deserializer for odd-ratio parallel data bus

摘要

A serializer and deserializer for an odd ratio parallel data bus are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits operate with a half rate clock to provide a full clock rate serial data stream. Providing a half-rate clock saves power and area for an integrated circuit incorporating a serializer. In addition, the bus conforms to the MIPI C-PHY standard by providing a 7: 1 serializer.