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Serializer and deserializer for odd ratio parallel data bus
Serializer and deserializer for odd ratio parallel data bus
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机译:奇数比并行数据总线的串行器和解串器
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摘要
Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
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