Allocation and issue stages for reordering microinstruction sequences into optimized microinstruction sequences to implement an instruction set agnostic runtime architecture

摘要

A system for an agnostic runtime architecture. The system includes a system emulation / virtualization converter, an application code converter, and a system converter. The system emulation / virtualization converter and the application code converter perform a system emulation process. Implement the system conversion process to execute the code from the guest image. The system converter includes an instruction fetch component for fetching an incoming microinstruction sequence, a decode component coupled to the instruction fetch component, receiving the fetched macroinstruction sequence and decoding it into a microinstruction sequence; Allocation and issue, coupled to a decoding component, receiving a microinstruction sequence and performing an optimization process by reordering the microinstruction sequence into an optimized microinstruction sequence including a plurality of dependency code groups And a stage. A microprocessor pipeline is coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence. A sequence cache is coupled to the allocation and issue stage and receives and stores a copy of the microinstruction sequence optimized for subsequent use in subsequent hits of the optimized microinstruction sequence, the hardware component Are combined to transfer instructions in the incoming microinstruction sequence. [Selection] Figure 7