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AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
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机译:用于将微指令序列重新排列为优化的微指令序列以实现指令集非运行时体系结构的分配和发布阶段
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摘要
A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises an instruction fetch component for fetching an incoming microinstruction sequence, a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence, and an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. A microprocessor pipeline is coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence. A sequence cache is coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence, and a hardware component is coupled for moving instructions in the incoming microinstruction sequence.
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