Static random access memory (SRAM) global bit line circuit and related methods and systems for reducing power glitches during memory read access

摘要

A static random access memory (SRAM) global bit line circuit and related methods and systems for reducing glitches during read access are disclosed. A global bit line scheme in SRAM can reduce output load and power consumption. In some embodiments, the SRAM includes an SRAM array. The SRAM includes a global bit line circuit for each SRAM array column. Each global bit line circuit includes a memory access circuit that precharges local bit lines corresponding to bit cells in the SRAM array. Data read from the selected bit cell is read from its local bit line onto an aggregated read bit line that is an aggregation of local bit lines. The SRAM includes a bit line evaluation circuit that sends data from the aggregated read bit line onto the global bit line. Rather than sending data based on the rising transition of the clock trigger, data is sent on the global bit line based on the falling transition of the clock trigger. A global bit line scheme that reduces glitches is utilized, which can result in increased power consumption.