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DESIGNING PROGRAM OF PROGRAMMABLE LOGIC DEVICE, PROGRAMMABLE LOGIC DEVICE DESIGNING APPARATUS, AND METHOD THEREOF

机译:可编程逻辑装置的设计程序,可编程逻辑装置设计装置及其方法

摘要

In the designing program of a programmable logic device, the logical expression of the combinational circuit is acquired from the arranged wire information on the programmable logic device. Next, a wire delay amount connected to an input port of the combinational circuit is acquired from the arranged wire information. Next, the input ports of the connection destinations of the wires connected to at least two input ports of the combinational circuit are exchanged so that the input order coincides with the input order corresponding to the logical expression of the combinational circuit stored in the input port change table. This processing is based on a cell delay amount of the combinational circuit and the wire delay amount. Then, the logical expression of the combinational circuit is changed in accordance with the exchange of the input ports of the connection destinations of the wires.
机译:在可编程逻辑器件的设计程序中,从在可编程逻辑器件上布置的布线信息中获取组合电路的逻辑表达式。接下来,从布置的布线信息中获取连接到组合电路的输入端口的布线延迟量。接下来,交换连接到组合电路的至少两个输入端口的电线的连接目的地的输入端口,使得输入顺序与对应于存储在输入端口改变中的组合电路的逻辑表达式的输入顺序一致。表。该处理基于组合电路的单元延迟量和布线延迟量。然后,根据电线的连接目的地的输入端口的交换来改变组合电路的逻辑表达式。

著录项

  • 公开/公告号US2017207787A1

    专利类型

  • 公开/公告日2017-07-20

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US201615352676

  • 发明设计人 YOSHINORI MESAKI;SHINICHIRO UEKUSA;

    申请日2016-11-16

  • 分类号H03K19/177;H03K19/173;

  • 国家 US

  • 入库时间 2022-08-21 13:51:50

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